The present invention relates to the field of integrated circuit memory technology. More specifically, the present invention provides a nonvolatile memory cell with multiple oxide thicknesses and techniques of operating, programming, erasing, evaluating characteristics of the memory cell, and enhancing the reliability and service life of the memory cell.
Memory cells are used in the implementation of many types of electronic devices and integrated circuits. These devices include microprocessors, static random access memories (SRAMs), erasable-programmable read only memories (EPROMs), electrically erasable programmable read only memories (EEPROMs), Flash EEPROM memories, programmable logic devices (PLDs), field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), among others. Memory cells are used to store the data and other information for these and other integrated circuits.
As integrated circuit technology and semiconductor processing continue to advance, there is a need for greater densities and functionality in integrated circuits, which are often determined in a large part by the size of the memory cells. Further, it is desirable that the memory cells have improved operating characteristics, such as lower power consumption, nonvolatility, greater device longevity, improved data retention, better transient performance, superior voltage and current attributes, and improvements in other similar attributes.
There is a need to provide techniques for programming and erasing the memory cells reliably. For example, during the program operation, memory cells which are not to be programmed should be left undisturbed. There is further a need for improved techniques of evaluating the physical characteristics of nonvolatile memory cells. These physical characteristics or properties are important in the determination of an integrated circuit""s service life and reliability. These measurements are also useful for study and use in improving memory cells. One property of a memory cell is margin, including program and erase margin, indicating the degree to which a cell is in a programmed or erased state. The degree of margin comes from a determination of the threshold voltages in the programmed and erased states. In particular, the voltage threshold (VTE) of erased nonvolatile memory cells such as EEPROM or Flash cells may be negative.
As can be seen, improved memory cells and techniques for operating, programming, erasing, and evaluating characteristics of these cells are needed. Improved techniques are also needed for improving the reliability and longevity of these memory devices.
The present invention provides a nonvolatile memory cell with multiple oxide thicknesses. The memory cell of the present invention may be used to form compact arrays of memory cells to store logical data. During programming of a selected memory cell, unselected memory cells are not disturbed, and oxide stress for the unselected memory cells is minimized. The present invention also provides techniques for operating, programming, erasing, and characterizing the memory cell with multiple oxide thicknesses. Erased nonvolatile memory cells of the present invention may have negative threshold voltages in some implementations. The techniques of the present invention may be used to measure these negative values.
Specifically, the memory cell of the present invention includes: a floating gate; a tunnel oxide beneath the floating gate to facilitate transfer of charge from the floating gate; and a thick oxide beneath the floating gate to prevent disturb effects, where the memory cell retains its stored state when another memory cell coupled to the memory cell is programmed. The tunnel oxide thickness is thinner than the thick oxide thickness. Furthermore, for the memory cell, hot electrons pass through the thick oxide when a programming current is induced from a first n+ region to a second n+ region.
The memory cell of the present invention includes a first oxide portion having a first oxide thickness to permit transfer of charge from a floating gate by tunneling. And, the memory cell further includes a second oxide portion having a second oxide thickness to prevent disturbing of state of the floating gate during operation of the memory cells, while allowing hot electron transfer to the floating gate during programming, where the first oxide portion and second oxide portion are beneath the floating gate.
Furthermore, the present invention provides techniques for operating the memory cell having multiple oxide thicknesses using an elevated source voltage. A voltage of about 2 volts may be coupled to the source of the memory cell to facilitate decoupling of the memory cell during program, erase, or evaluation of margin. Furthermore, the use of elevated source voltages may be used to facilitate the measurement of negative erased threshold voltages, and during the normal operation to adjust a VT window of the memory cells.
Other objects, features, and advantages of the present invention will become apparent upon consideration of the following detailed description and the accompanying drawings, in which like reference designations represent like features throughout the figures.